1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More specifically, it relates to a nonvolatile semiconductor memory, which uses a metallic salicide film as an electrode film.
2. Description of the Related Art
An electrically data-erasable programmable read-only memory (EEPROM) is known as a nonvolatile semiconductor memory. The EEPROM, in particular, a NAND EEPROM includes a memory cell array comprised of memory cells disposed on respective intersections of horizontal word lines and vertical bit lines. Typically, a memory cell is structured by, for example, a MOS transistor having a stacked gate structure of a floating gate and a control gate.
A NAND flash memory has a structure where multiple memory cell transistors are connected in series to constitute a NAND string, and select transistors are disposed on both sides of the NAND string. In addition, a memory cell array is arranged with an element isolating region (STI) in parallel with an element activation region of a memory cell.
A nonvolatile semiconductor memory, such as a flash EEPROM, requires a high voltage circuit region for providing high voltage pulses, such as a write-in voltage, an intermediate voltage, and an erase voltage, to a memory cell array region. In addition, there is a typical low voltage circuit region to which low voltage pulses are provided and for which high-speed performance is required.
However, in a low voltage circuit region, use of a high-speed transistor with higher driving capability is advantageous. More specifically, in a low voltage circuit region of a flash EEPROM capable of low power supply voltage operation, transistors are required to have a sufficient driving capability in order to realize a high speed performance. On the other hand, an increase in capacity of a memory cell array requires a decrease in word line resistance in a memory cell region, so as to increase writing/reading speed. Forming a metallic salicide film on a word line in a NAND flash memory is a technique for preventing a word line delay due to increased capacity and increasing the operating speed.
A low voltage circuit region needs to include a higher-speed transistor with higher driving capability. Forming a metallic salicide film in a gate and a diffusion layer decreases word line resistance in a memory cell region of a large capacity memory cell array and increases writing/reading speed.
However, as with CMOS logic, in the case where a metallic salicide film is formed on gates and diffusion layers in an entire circuit region of a nonvolatile semiconductor memory, such as a flash EEPROM, it is important to prevent an increase in junction leakage and degradation in junction breakdown voltage and surface breakdown voltage in a transistor fabricated within a high voltage circuit region. The high voltage circuit region provides high voltage pulses of 15 V or greater, such as programming voltage Vpgm and erase voltage Verase. In addition, a decrease in resistance of a resistive element may require an increase in element area and degradation in the gate breakdown voltage of a transistor in the high voltage peripheral circuit. Forming a metallic salicide film on a selected region may solve the aforementioned problems, however, the metallic salicide film may cause increased difficulty in device fabrication, due to the metallic salicide film.
In particular, since the NAND structure requires a higher voltage than that for the AND and the NOR structure, and increases junction leakage and junction breakdown voltage.
According to a nonvolatile semiconductor memory and a fabrication method for the same, disclosed in Japanese Patent Application Laid-Open No. 2000-100975, a trench is formed, extending along the word line length, on a control gate, a metallic interconnect is formed on an interlayer insulating film, and the metallic interconnect is filled in the trench, thereby decreasing the resistance of a polycide word line. This structure decreases word line resistance and reduces memory reading duration without complicating the fabrication process.
According to a semiconductor memory and a fabrication method for the same, in Japanese Patent Application Laid-Open No. 2003-347511, silicide layers are not formed on the top surface of an impurity diffusion layer in a memory cell transistor. Instead, a silicide layer is formed on a gate electrode, and a silicide layer is formed on the gate electrode and the diffusion layer in a logic region, so as to increase the operating speed of the device.